Strained-semiconductor-on-insulator device structures

ABSTRACT

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. ProvisionalApplication No. 60/386,968 filed Jun. 7, 2002 and U.S. ProvisionalApplication No. 60/404,058 filed Aug. 15, 2002; the entire disclosuresof both provisional applications are hereby incorporated by reference.

FIELD OF THE INVENTION

[0002] This invention relates to devices and structures comprisingstrained semiconductor layers and insulator layers.

BACKGROUND

[0003] Strained silicon-on-insulator structures for semiconductordevices combine the benefits of two advanced approaches to performanceenhancement: silicon-on-insulator (SOI) technology and strained silicon(Si) technology. The strained silicon-on-insulator configuration offersvarious advantages associated with the insulating substrate, such asreduced parasitic capacitances and improved isolation. Strained Siprovides improved carrier mobilities. Devices such as strained Simetal-oxide-semiconductor field-effect transistors (MOSFETs) combineenhanced carrier mobilities with the advantages of insulatingsubstrates.

[0004] Strained-silicon-on-insulator substrates are typically fabricatedas follows. First, a relaxed silicon-germanium (SiGe) layer is formed onan insulator by one of several techniques such as separation byimplantation of oxygen (SIMOX), wafer bonding and etch back; waferbonding and hydrogen exfoliation layer transfer; or recrystallization ofamorphous material. Then, a strained Si layer is epitaxially grown toform a strained-silicon-on-insulator structure, with strained Sidisposed over SiGe. The relaxed-SiGe-on-insulator layer serves as thetemplate for inducing strain in the Si layer. This induced strain istypically greater than 10⁻³. This structure has limitations. It is notconducive to the production of fully-depletedstrained-semiconductor-on-insulator devices in which the layer over theinsulating material must be thin enough [<300 angstroms (Å)] to allowfor full depletion of the layer during device operation. Fully depletedtransistors may be the favored version of SOI for MOSFET technologiesbeyond the 90 nm technology node. The relaxed SiGe layer adds to thetotal thickness of this layer and thus makes it difficult to achieve thethicknesses required for fully depleted silicon-on-insulator devicefabrication. The relaxed SiGe layer is not required if a strained Silayer can be produced directly on the insulating material. Thus, thereis a need for a method to produce strained silicon—or othersemiconductor—layers directly on insulating substrates.

SUMMARY

[0005] The present invention includes astrained-semiconductor-on-insulator (SSOI) substrate structure andmethods for fabricating the substrate structure. MOSFETs fabricated onthis substrate will have the benefits of SOI MOSFETs as well as thebenefits of strained Si mobility enhancement. By eliminating the SiGerelaxed layer traditionally found beneath the strained Si layer, the useof SSOI technology is simplified. For example, issues such as thediffusion of Ge into the strained Si layer during high temperatureprocesses are avoided.

[0006] This approach enables the fabrication of well-controlled,epitaxially-defined, thin strained semiconductor layers directly on aninsulator layer. Tensile strain levels of ˜1% or greater are possible inthese structures, and are not diminished after thermal anneal cycles. Insome embodiments, the strain-inducing relaxed layer is not present inthe final structure, eliminating some of the key problems inherent tocurrent strained Si-on-insulator solutions. This fabrication process issuitable for the production of enhanced-mobility substrates applicableto partially or fully depleted SSOI technology.

[0007] In an aspect, the invention features a structure that includes afirst substrate having a dielectric layer disposed thereon, and a firststrained semiconductor layer disposed in contact with the dielectriclayer.

[0008] One or more of the following features may be included. Thestrained semiconductor layer may include at least one of a group II, agroup III, a group IV, a group V, and a group VI element, such assilicon, germanium, silicon germanium, gallium arsenide, indiumphosphide, or zinc selenide. The strained semiconductor layer may besubstantially free of germanium, and any other layer disposed in contactwith the strained semiconductor layer may be substantially free ofgermanium. The strained semiconductor layer may be tensilely strained orcompressively strained. The strained semiconductor layer may have astrained portion and a relaxed portion.

[0009] A second strained semiconductor layer may be in contact with thefirst strained semiconductor layer. The first strained semiconductorlayer may be compressively strained and the second strainedsemiconductor layer may be tensilely strained, or vice versa.

[0010] The structure may include a transistor having a source region anda drain region disposed in a portion of the strained semiconductorlayer, a gate disposed above the strained semiconductor layer andbetween the source and drain regions, and a gate dielectric layerdisposed between the gate and the strained semiconductor layer.

[0011] The strained semiconductor layer may have been formed on a secondsubstrate, may have been disposed in contact with the dielectric layerby bonding, and may have a lower dislocation density than an initialdislocation density of the strained semiconductor layer as formed. Theinitial dislocation density may have been lowered by etching. Thestrained semiconductor layer may have been grown with an initialdislocation density and may have a dislocation density less than theinitial dislocation density. The strained semiconductor layer may havebeen formed by epitaxy. The strained semiconductor layer may have athickness uniformity of better than approximately ±5%. The strainedlayer has a thickness selected from a range of approximately 20angstroms-1000 angstroms. The strained layer has a surface roughness ofless than approximately 20 angstroms. The substrate may include siliconand/or germanium.

[0012] In another aspect, the invention features a structure including arelaxed substrate including a bulk material, and a strained layerdisposed in contact with the relaxed substrate. The strain of thestrained layer is not induced by the underlying substrate, and thestrain is independent of a lattice mismatch between the strained layerand the relaxed substrate. The bulk material may include a firstsemiconductor material. The strained layer may include a secondsemiconductor material. The first semiconductor material may beessentially the same as the second semiconductor material. The first andsecond semiconductor material may include silicon. A lattice constant ofthe relaxed substrate may be equal to a lattice constant of the strainedlayer in the absence of strain. The strain of the strained layer may begreater than approximately 1×10⁻³. The strained layer may have beenformed by epitaxy. The strained layer may have a thickness uniformity ofbetter than approximately ±5%. The strained layer may have a thicknessselected from a range of approximately 20 angstroms-1000 angstroms. Thestrained layer may have a surface roughness of less than approximately20 angstroms.

[0013] The structure may include a transistor having a source region anda drain region disposed in a portion of the strained semiconductorlayer, a gate contact disposed above the strained semiconductor layerand between the source and drain regions, and a gate dielectric layerdisposed between the gate contact and the strained semiconductor layer.

[0014] In another aspect, the invention features a structure including asubstrate including a dielectric material, and a strained semiconductorlayer disposed in contact with the dielectric material.

[0015] One or more of the following features may be included. Thedielectric material may include sapphire. The semiconductor layer mayhave been formed on a second substrate, have been disposed in contactwith the dielectric material by bonding, and have a lower dislocationdensity than an initial dislocation density of the semiconductor layeras formed. The initial dislocation density may have been lowered byetching. The semiconductor layer may have been formed by epitaxy.

[0016] In another aspect, the invention features a method for forming astructure, the method including providing a first substrate having afirst strained semiconductor layer formed thereon, bonding the firststrained semiconductor layer to an insulator layer disposed on a secondsubstrate and, removing the first substrate from the first strainedsemiconductor layer, the strained semiconductor layer remaining bondedto the insulator layer.

[0017] One or more of the following features may be included. Thestrained semiconductor layer may be tensilely or compressively strained.The strained semiconductor layer may include a surface layer or a buriedlayer after the removal of the first substrate.

[0018] Removing the first substrate from the strained semiconductorlayer may include cleaving. Cleaving may include implantation of anexfoliation species through the strained semiconductor layer to initiatecleaving. The exfoliation species may include at least one of hydrogenand helium. Providing the first substrate may include providing thefirst substrate having a second strained layer disposed between thesubstrate and the first strained layer, the second strained layer actingas a cleave plane during cleaving. The second strained layer may includea compressively strained layer. The compressively strained layer mayinclude S_(1−x)Ge_(x). The first substrate may have a relaxed layerdisposed between the substrate and the first strained layer.

[0019] The relaxed layer may be planarized prior to forming the firststrained semiconductor layer. After the relaxed layer is planarized, arelaxed semiconductor regrowth layer may be formed thereon. A dielectriclayer may be formed over the first strained semiconductor layer prior tobonding the first strained semiconductor layer to an insulator layer.Removing the first substrate from the strained semiconductor layer mayinclude mechanical grinding. Bonding may include achieving a high bondstrength, e.g., greater than or equal to about 1000 milliJoules/metersquared (mJ/m²), at a low temperature, e.g., less than approximately600° C.

[0020] Bonding may include plasma activation of a surface of the firstsemiconductor layer prior to bonding the first semiconductor layer.Plasma activation may include use of at least one of an ammonia (NH₃),an oxygen (O₂), an argon (Ar), and a nitrogen (N₂) source gas. Bondingmay include planarizing a surface of the first semiconductor layer priorto bonding the first semiconductor layer by, e.g., chemical-mechanicalpolishing. A portion of the first strained semiconductor layer may berelaxed such as by, e.g., introducing a plurality of ions into theportion of the first strained semiconductor layer.

[0021] A transistor may be formed by forming a gate dielectric layerabove a portion of the strained semiconductor layer, forming a gatecontact above the gate dielectric layer, and forming a source region anda drain region in a portion of the strained semiconductor layer,proximate the gate dielectric layer.

[0022] In another aspect, the invention features a method for forming astructure, the method including providing a substrate having a relaxedlayer disposed over a first strained layer, the relaxed layer inducingstrain in the first strained layer, and removing at least a portion ofthe relaxed layer selectively with respect to the first strained layer.

[0023] One or more of the following features may be included. The firststrained layer may be bonded to the substrate, including, e.g., to aninsulator layer disposed on the substrate. The first strained layer maybe formed over the relaxed layer on another substrate. The portion ofthe relaxed layer may be removed by, e.g., oxidation, a wet chemicaletch, a dry etch, and/or chemical-mechanical polishing. After removal ofat least a portion of the relaxed layer, the strained layer may beplanarized by, e.g., chemical-mechanical polishing and/or an anneal. Theanneal may be performed at a temperature greater than 800° C.

[0024] The substrate may have an etch stop layer disposed between therelaxed layer and the strained layer. The etch stop layer may becompressively strained. The strained layer may include silicon, therelaxed layer may include silicon germanium, and the etch stop layer mayinclude silicon germanium carbon. The relaxed layer may includeSi_(1−y)Ge_(y), the etch stop layer may include Si_(1−x)Ge_(x), and xmay be greater than y, e.g., x may be approximately 0.5 and y may beapproximately 0.2. The etch stop layer enables an etch selectivity tothe relaxed layer of greater than 10:1, e.g., greater than 100:1. Theetch stop layer may have a thickness selected from a range of about 20angstroms to about 1000 angstroms. The relaxed layer may be formed overa graded layer.

[0025] In another aspect, the invention features a method for forming astructure, the method including providing a first substrate having adielectric layer disposed thereon, and forming a semiconductor layer ona second substrate, the semiconductor layer having an initial misfitdislocation density. The semiconductor layer is bonded to the dielectriclayer, and the second substrate is removed, the semiconductor layerremaining bonded to the dielectric layer. The misfit dislocation densityin the semiconductor layer is reduced.

[0026] One or more of the following features may be included. The misfitdislocation density may be reduced by removing a portion of thesemiconductor layer, such as, e.g., by etching. After removing a portionof the semiconductor layer to reduce misfit dislocation density, aregrowth layer may be formed over the semiconductor layer withoutincreasing misfit dislocation density. The regrowth layer may be formedby epitaxy.

[0027] In another aspect, the invention features a method for forming astructure, the method including providing a first substrate having adielectric layer disposed thereon, forming a semiconductor layer on asecond substrate, the semiconductor layer having an initial misfitdislocation density. The semiconductor layer is bonded to the dielectriclayer. The second substrate is removed, the semiconductor layerremaining bonded to the dielectric layer, and a regrowth layer is grownover the semiconductor layer.

[0028] One or more of the following features may be included. Thesemiconductor layer and the regrowth layer may include the samesemiconductor material. The semiconductor layer and the regrowth layertogether may have a misfit dislocation density not greater than theinitial misfit dislocation density.

[0029] In another aspect, the invention features a method for forming astructure, the method including providing a first substrate having astrained layer disposed thereon, the strained layer including a firstsemiconductor material, and bonding the strained layer to a secondsubstrate, the second substrate including a bulk material. The firstsubstrate is removed from the strained layer, the strained layerremaining bonded to the bulk semiconductor material. The strain of thestrained layer is not induced by the second substrate and the strain isindependent of lattice mismatch between the strained layer and thesecond substrate.

[0030] One or more of the following features may be included. The bulkmaterial may include a second semiconductor material. The firstsemiconductor material may be substantially the same as the secondsemiconductor material. The second substrate and/or the strainedsemiconductor layer may include silicon.

[0031] In another aspect, the invention features a method for forming astructure, the method including providing a first substrate having asemiconductor layer disposed over a strained layer. The semiconductorlayer is bonded to an insulator layer disposed on a second substrate,and the first substrate is removed from the strained layer, thesemiconductor layer remaining bonded to the insulator layer.

[0032] One or more of the following features may be included. Thesemiconductor layer may be substantially relaxed. The semiconductorlayer and/or the strained layer may include at least one of a group II,a group III, a group IV, a group V, and a group VI element. Thesemiconductor layer may include germanium and the strained layer mayinclude silicon.

BRIEF DESCRIPTION OF DRAWINGS

[0033] FIGS. 1A-6 are schematic cross-sectional views of substratesillustrating a method for fabricating an SSOI substrate;

[0034]FIG. 7 is a schematic cross-sectional view illustrating analternative method for fabricating the SSOI substrate illustrated inFIG. 6;

[0035]FIG. 8 is a schematic cross-sectional view of a transistor formedon the SSOI substrate illustrated in FIG. 6;

[0036] FIGS. 9-10 are schematic cross-sectional views of substrate(s)illustrating a method for fabricating an alternative SSOI substrate;

[0037]FIG. 11 is a schematic cross-sectional view of a substrate havingseveral layers formed thereon;

[0038] FIGS. 12-13 are schematic cross-sectional views of substratesillustrating a method for fabricating an alternative strainedsemiconductor substrate; and

[0039]FIG. 14 is a schematic cross-sectional view of the SSOI substrateillustrated in FIG. 6 after additional processing.

[0040] Like-referenced features represent common features incorresponding drawings.

DETAILED DESCRIPTION

[0041] An SSOI structure may be formed by wafer bonding followed bycleaving. FIGS. 1A-2B illustrate formation of a suitable strained layeron a wafer for bonding, as further described below.

[0042] Referring to FIG. 1A, an epitaxial wafer 8 has a plurality oflayers 10 disposed over a substrate 12. Substrate 12 may be formed of asemiconductor, such as Si, Ge, or SiGe. The plurality of layers 10includes a graded buffer layer 14, which may be formed ofSi_(1−y)Ge_(y), with a maximum Ge content of, e.g., 20-70% (i.e.,y=0.2-0.7) and a thickness T₁ of, for example, 2-7 micrometers (μm). Arelaxed layer 16 is disposed over graded buffer layer 14. Relaxed layer16 may be formed of uniform Si_(1−x)Ge_(x) having a Ge content of, forexample, 20-70% (i.e., x=0.2-0.7), and a thickness T₂ of, for example,0.2-2 μm. In some embodiments, Si_(1−x)Ge_(x) may includeSi_(0.70)Ge_(0.30) and T₂ may be approximately 1.5 μm. Relaxed layer 16may be fully relaxed, as determined by triple axis X-ray diffraction,and may have a threading dislocation density of <1×10⁶ cm⁻², asdetermined by etch pit density (EPD) analysis.

[0043] Substrate 12, graded layer 14, and relaxed layer 16 may be formedfrom various materials systems, including various combinations of groupII, group III, group IV, group V, and group VI elements. For example,each of substrate 12, graded layer 14, and relaxed layer 16 may includea III-V compound. Substrate 12 may include gallium arsenide (GaAs),graded layer 14 and relaxed layer 16 may include indium gallium arsenide(InGaAs) or aluminum gallium arsenide (AlGaAs). These examples aremerely illustrative, and many other material systems are suitable.

[0044] A strained semiconductor layer 18 is disposed over relaxed layer16. Strained layer 18 may include a semiconductor such as at least oneof a group II, a group III, a group IV, a group V, and a group VIelement. Strained semiconductor layer 18 may include, for example, Si,Ge, SiGe, GaAs, indium phosphide (InP), and/or zinc selenide (ZnSe).Strained layer 18 has a thickness T₃ of, for example, 50-1000 Å. In anembodiment, T₃ may be approximately 200-500 Å. Strained layer 18 may beformed by epitaxy, such as by atmospheric-pressure CVD (APCVD), low- (orreduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHVCVD), or bymolecular beam epitaxy (MBE). The epitaxial growth system may be asingle-wafer or multiple-wafer batch reactor. The growth system may alsoutilize a low-energy plasma to enhance layer growth kinetics. Afterformation, strained layer 18 has an initial misfit dislocation density,of, for example, 0-10⁵ cm⁻¹. In one embodiment, strained layer 18 istensilely strained. In another embodiment, strained layer 18 iscompressively strained.

[0045] In alternative embodiments, graded layer 14 may be absent fromthe structure. Relaxed layer 16 may be formed in various ways, and theinvention is not limited to embodiments having graded layer 14. In otherembodiments, strained layer 18 may be formed directly on substrate 12.In this case, the strain in layer 18 may be induced by lattice mismatchbetween layer 18 and substrate 12, induced mechanically, e.g., by thedeposition of overlayers, such as Si₃N₄, or induced by thermal mismatchbetween layer 18 and a subsequently grown layer, such as a SiGe layer.In some embodiments, a uniform semiconductor layer (not shown), having athickness of approximately 0.5 μm and comprising the same semiconductormaterial as substrate 12, is disposed between graded buffer layer 14 andsubstrate 12. This uniform semiconductor layer may be grown to improvethe material quality of layers subsequently grown on substrate 12, suchas graded buffer layer 14, by providing a clean, contaminant-freesurface for epitaxial growth. In certain embodiments, relaxed layer 16may be planarized prior to growth of strained layer 18 to eliminate thecrosshatched surface roughness induced by graded buffer layer 14. (See,e.g., M. T. Currie, et al., Appl. Phys. Lett., 72 (14) p. 1718 (1998),incorporated herein by reference.) The planarization may be performed bya method such as chemical mechanical polishing (CMP), and may improvethe quality of a subsequent bonding process (see below) because itminimizes the wafer surface roughness and increases wafer flatness, thusproviding a greater surface area for bonding.

[0046] Referring to FIG. 1B, after planarization of relaxed layer 16, arelaxed semiconductor regrowth layer 19 including a semiconductor suchas SiGe may be grown on relaxed layer 16, thus improving the quality ofsubsequent strained layer 18 growth by ensuring a clean surface for thegrowth of strained layer 18. Growing on this clean surface may bepreferable to growing strained material, e.g., silicon, on a surfacethat is possibly contaminated by oxygen and carbon from theplanarization process. The conditions for epitaxy of the relaxedsemiconductor regrowth layer 19 on the planarized relaxed layer 16should be chosen such that surface roughness of the resulting structure,including layers formed over regrowth layer 19, is minimized to ensure asurface suitable for subsequent high quality bonding. High qualitybonding may be defined as the existence of a bond between two wafersthat is substantially free of bubbles or voids at the interface.Measures that may help ensure a smooth surface for strained layer 18growth, thereby facilitating bonding, include substantially matching alattice of the semiconductor regrowth layer 19 to that of the underlyingrelaxed layer 16, by keeping the regrowth thickness below approximately1 μm, and/or by keeping the growth temperature below approximately 850°C. for at least a portion of the semiconductor layer 19 growth. It mayalso be advantageous for relaxed layer 16 to be substantially free ofparticles or areas with high threading dislocation densities (i.e.,threading dislocation pile-ups) which could induce non-planarity in theregrowth and decrease the quality of the subsequent bond.

[0047] Referring to FIG. 2A, in an embodiment, hydrogen ions areimplanted into relaxed layer 16 to define a cleave plane 20. Thisimplantation is similar to the SMARTCUT process that has beendemonstrated in silicon by, e.g., SOITEC, based in Grenoble, France.Implantation parameters may include implantation of hydrogen (H₂ ⁺) to adose of 3-5×10¹⁶/cm² at an energy of, e.g., 50-100 keV. For example, H₂⁺ may be implanted at an energy of 75 keV and a dose of 4×10¹⁶/cm²through strained layer 18 into relaxed layer 16. In alternativeembodiments, it may be favorable to implant at energies less than 50 keVto decrease the depth of cleave plane 20 and decrease the amount ofmaterial subsequently removed during the cleaving process (seediscussion below with reference to FIG. 4). In an alternativeembodiment, other implanted species may be used, such as H⁺ or He⁺, withthe dose and energy being adjusted accordingly. The implantation mayalso be performed prior to the formation of strained layer 18. Then, thesubsequent growth of strained layer 18 is preferably performed at atemperature low enough to prevent premature cleaving along cleave plane20, i.e., prior to the wafer bonding process. This cleaving temperatureis a complex function of the implanted species, implanted dose, andimplanted material. Typically, premature cleaving may be avoided bymaintaining a growth temperature below approximately 500° C.

[0048] In some embodiments, strained layer 18 may be planarized by,e.g., CMP, to improve the quality of the subsequent bond. Referring toFIG. 2B, in some embodiments, a dielectric layer 22 may be formed overstrained layer 18 prior to ion implantation into relaxed layer 16 toimprove the quality of the subsequent bond. Dielectric layer 22 may be,e.g., silicon dioxide (SiO₂) deposited by, for example, LPCVD or by highdensity plasma (HDP). An LPCVD deposited SiO₂ layer may be subjected toa densification step at elevated temperature. Suitable conditions forthis densification step can be a 10 minute anneal at 800° C. in anitrogen ambient. Dielectric layer 22 may be planarized by, e.g., CMP toimprove the quality of the subsequent bond. In an alternativeembodiment, it may be advantageous for dielectric layer 22 to be formedfrom thermally grown SiO₂ in order to provide a high qualitysemiconductor/dielectric interface in the final structure.

[0049] Referring to FIG. 3, epitaxial wafer 8 is bonded to a handlewafer 50. Either handle wafer 50, epitaxial wafer 8, or both have a topdielectric layer (see, e.g., dielectric layer 22 in FIG. 2B) tofacilitate the bonding process and to serve as an insulator layer in thefinal substrate structure. Handle wafer 50 may have a dielectric layer52 disposed over a semiconductor substrate 54. Dielectric layer 52 mayinclude, for example, SiO₂, silicon nitride (Si₃N₄), aluminum oxide,etc. In other embodiments, handle wafer 50 may comprise a combination ofa bulk semiconductor material and a dielectric layer, such as a siliconon insulator substrate. Semiconductor substrate 54 includes asemiconductor material such as, for example, Si, Ge, or SiGe. Handlewafer 50 and epitaxial wafer 8 are cleaned by a wet chemical cleaningprocedure to facilitate bonding, such as by a hydrophilic surfacepreparation process to assist the bonding of a semiconductor material,e.g., strained layer 18, to a dielectric material, e.g., dielectriclayer 52. For example, a suitable prebonding surface preparationcleaning procedure could include a modified megasonic RCA SC1 cleancontaining ammonium hydroxide, hydrogen peroxide, and water(NH₄OH:H₂O₂:H₂O) at a ratio of 1:4:20 at 60° C. for 10 minutes, followedby a deionized (DI) water rinse and spin dry. The wafer bonding energyshould be strong enough to sustain the subsequent layer transfer (seeFIG. 4). In some embodiments, top surfaces 60, 62 of handle wafer 50 andepitaxial wafer 8, including a top surface 63 of strained semiconductorlayer 18, may be subjected to a plasma activation, either before, after,or instead of a wet clean, to increase the bond strength. The plasmaenvironment may include at least one of the following species: oxygen,ammonia, argon, and nitrogen. After an appropriate cleaning step, handlewafer 50 and epitaxial wafer 8 are bonded together by bringing topsurfaces 60, 62 in contact with each other at room temperature. The bondstrength may be greater than 1000 mJ/m², achieved at a low temperature,such as less than 600° C.

[0050] Referring to FIG. 4 as well as to FIG. 3, a split is induced atcleave plane 20 by annealing handle wafer 50 and epitaxial wafer 8 afterthey are bonded together. This split may be induced by an anneal at300-700° C., e.g., 550° C., inducing hydrogen exfoliation layer transfer(i.e., along cleave plane 20) and resulting in the formation of twoseparate wafers 70, 72. One of these wafers (70) has a first portion 80of relaxed layer 16 (see FIG. 1A) disposed over strained layer 18.Strained layer 18 is in contact with dielectric layer 52 onsemiconductor substrate 54. The other of these wafers (72) includessilicon substrate 12, graded layer 14, and a remaining portion 82 ofrelaxed layer 16. If necessary, wafer 70 with strained layer 18 may beannealed further at 600-900° C., e.g., at a temperature greater than800° C., to strengthen the bond between the strained layer 18 anddielectric layer 52. In some embodiments, this anneal is limited to anupper temperature of about 900° C. to avoid the destruction of astrained Si/relaxed SiGe heterojunction by diffusion. Wafer 72 may beplanarized, and used as starting substrate 8 for growth of anotherstrained layer 18. In this manner, wafer 72 may be “recycled” and theprocess illustrated in FIGS. 1A-5 may be repeated.

[0051] Referring to FIG. 4 as well as to FIG. 5, relaxed layer portion80 is removed from strained layer 18. Relaxed layer portion 80,including, e.g., SiGe, is oxidized by wet (steam) oxidation. Forexample, at temperatures below approximately 800° C., such astemperatures between 600-750° C., wet oxidation will oxidize SiGe muchmore rapidly then Si, such that the oxidation front will effectivelystop when it reaches the strained layer 18, in embodiments in whichstrained layer 18 includes Si. The difference between wet oxidationrates of SiGe and Si may be even greater at lower temperatures, such asapproximately 400° C.-600° C. Good oxidation selectivity is provided bythis difference in oxidation rates, i.e., SiGe may be efficientlyremoved at low temperatures with oxidation stopping when strained layer18 is reached. This wet oxidation results in the transformation of SiGeto a thermal insulator 90, e.g., Si_(x)Ge_(y)O_(z). The thermalinsulator 90 resulting from this oxidation is removed in a selective wetor dry etch, e.g., wet hydrofluoric acid. In some embodiments, it may bemore economical to oxidize and strip several times, instead of justonce.

[0052] In certain embodiments, wet oxidation may not completely removethe relaxed layer portion 80. Here, a localized rejection of Ge mayoccur during oxidation, resulting in the presence of a residual Ge-richSiGe region at the oxidation front, on the order of, for example,several nanometers in lateral extent. A surface clean may be performedto remove this residual Ge. For example, the residual Ge may be removedby a dry oxidation at, e.g., 600° C., after the wet oxidation and stripdescribed above. Another wet clean may be performed in conjunctionwith—or instead of—the dry oxidation. Examples of possible wet etchesfor removing residual Ge include a Piranha etch, i.e., a wet etch thatis a mixture of sulfuric acid and hydrogen peroxide (H₂SO₄:H₂O₂) at aratio of 3:1. An HF dip may be performed after the Piranha etch.Alternatively, an RCA SC1 clean may be used to remove the residual Ge.The process of Piranha or RCA SC1 etching and HF removal of resultingoxide may be repeated more than once.

[0053] In an embodiment, after cleaving and prior to removal of relaxedlayer portion 80 by, e.g., wet oxidation, a CMP step may be performed toremove part of relaxed layer portion 80 as well as to increase thesmoothness of its surface. A smoother surface will improve theuniformity of subsequent complete removal by, e.g., wet oxidation.

[0054] After removal of relaxed layer portion 80, strained layer 18 maybe planarized. Planarization of strained layer 18 may be performed by,e.g., CMP or an anneal at a temperature greater than, for example, 800°C.

[0055] Referring to FIG. 6, a SSOI substrate 100 has strained layer 18disposed over an insulator, such as dielectric layer 52 formed onsemiconductor substrate 54. Strained layer 18 has a thickness T₄selected from a range of, for example, 20-1000 Å, with a thicknessuniformity of better than approximately ±5% and a surface roughness ofless than approximately 20 Å. Dielectric layer 52 has a thickness T₅₂selected from a range of, for example, 500-3000 Å. In an embodiment, themisfit dislocation density of strained layer 18 may be lower than itsinitial dislocation density. The initial dislocation density may belowered by, for example, performing an etch of a top surface 92 ofstrained layer 18. This etch may be a wet etch, such as a standardmicroelectronics clean step such as an RCA SC1, i.e., hydrogen peroxide,ammonium hydroxide, and water (H₂O₂+NH₄OH+H₂O), which at, e.g., 80° C.may remove silicon. In some embodiments, strained semiconductor layer 18includes Si and is substantially free of Ge; further, any other layerdisposed in contact with strained semiconductor layer 18, e.g.,dielectric layer 52, is also substantially free of Ge.

[0056] Referring to FIG. 7, in an alternative embodiment, relaxed layerportion 80 may be removed by a selective wet etch which stops at thestrained layer 18 to obtain SSOI substrate 100 (see FIG. 6). Inembodiments in which relaxed layer portion 80 contains SiGe, a suitableselective SiGe wet etch may be a mixture of hydrofluoric acid, hydrogenperoxide, and acetic acid (HF:H₂O₂:CH₃COOH), at a ratio of 1:2:3.Alternatively, relaxed layer portion 80 may be removed by a dry etchwhich stops at strained layer 18. In some embodiments, relaxed layerportion 80 may be removed completely or in part by a chemical-mechanicalpolishing step or by mechanical grinding.

[0057] Strained semiconductor-on-insulator substrate 100 may be furtherprocessed by CMOS SOI MOSFET fabrication methods. For example, referringto FIG. 8, a transistor 200 may be formed on SSOI substrate 100. Formingtransistor 200 includes forming a gate dielectric layer 210 abovestrained layer 18 by, for example, growing an SiO₂ layer by thermaloxidation. Alternatively, gate dielectric layer 210 may include a high-kmaterial with a dielectric constant higher than that of SiO₂, such ashafnium oxide (HfO₂)or hafnium silicate (HfSiON, HfSiO₄). In someembodiments, gate dielectric layer 210 may be a stacked structure, e.g.,a thin SiO₂ layer capped with a high-k material. A gate 212 is formedover gate dielectric layer 210. Gate 212 may be formed of a conductivematerial, such as doped semiconductor, e.g., polycrystalline Si orpolycrystalline SiGe, or a metal. A source region 214 and a drain region216 are formed in a portion 218 of strained semiconductor layer 18,proximate gate dielectric layer 210. Source and drain regions 214, 216may be formed by, e.g., ion implantation of either n-type or p-typedopants.

[0058] In alternative embodiments, an SSOI structure may include,instead of a single strained layer, a plurality of semiconductor layersdisposed on an insulator layer. For example, referring to FIG. 9,epitaxial wafer 300 includes strained layer 18, relaxed layer 16, gradedlayer 14, and substrate 12. In addition, a semiconductor layer 310 isdisposed over strained layer 18. Strained layer 18 may be tensilelystrained and semiconductor layer 310 may be compressively strained. Inan alternative embodiment, strained layer 18 may be compressivelystrained and semiconductor layer 310 may be tensilely strained. Strainmay be induced by lattice mismatch with respect to an adjacent layer, asdescribed above, or mechanically. For example, strain may be induced bythe deposition of overlayers, such as Si₃N₄. In another embodiment,semiconductor layer 310 is relaxed. Semiconductor layer 310 includes asemiconductor material, such as at least one of a group II, a group III,a group IV, a group V, and a group VI element. Epitaxial wafer 300 isprocessed in a manner analogous to the processing of epitaxial wafer 8,as described with reference to FIGS. 1-7.

[0059] Referring also to FIG. 10, processing of epitaxial wafer 300results in the formation of SSOI substrate 350, having strained layer 18disposed over semiconductor layer 310. Semiconductor layer 310 is bondedto dielectric layer 52, disposed over substrate 54. As noted above withreference to FIG. 9, strained layer 18 may be tensilely strained andsemiconductor layer 310 may be compressively strained. Alternatively,strained layer 18 may be compressively strained and semiconductor layer310 may be tensilely strained. In some embodiments, semiconductor layer310 may be relaxed.

[0060] Referring to FIG. 11, in some embodiments, a thin strained layer84 may be grown between strained layer 18 and relaxed layer 16 to act asan etch stop during etching, such as wet etching. In an embodiment inwhich strained layer 18 includes Si and relaxed layer 16 includesSi_(1−y)Ge_(y), thin strained layer 84 may include Si_(1−x)Ge_(x), witha higher Ge content (x) than the Ge content (y) of relaxed layer 16, andhence be compressively strained. For example, if the composition of therelaxed layer 16 is 20% Ge (Si_(0.80)Ge_(0.20)), thin strained layer 84may contain 40% Ge (Si_(0.60)Ge_(0.40)) to provide a more robust etchstop. In other embodiments, a second strained layer, such as thinstrained layer 84 with higher Ge content than relaxed layer 16, may actas a preferential cleave plane in the hydrogen exfoliation/cleavingprocedure described above.

[0061] In an alternative embodiment, thin strained layer 84 may containSi_(1−x)Ge_(x), with lower Ge content than relaxed layer 16. In thisembodiment, thin strained layer 84 may act as a diffusion barrier duringthe wet oxidation process. For example, if the composition of relaxedlayer 16 is 20% Ge (Si_(0.80)Ge_(0.20)), thin strained layer 84 maycontain 10% Ge (Si_(0.90)Ge_(0.10)) to provide a barrier to Ge diffusionfrom the higher Ge content relaxed layer 16 during the oxidationprocess. In another embodiment, thin strained layer 84 may be replacedwith a thin graded Si_(1−z)Ge_(z) layer in which the Ge composition (z)of the graded layer is decreased from relaxed layer 16 to the strainedlayer 18.

[0062] Referring again to FIG. 7, in some embodiments, a small amount,e.g., approximately 20-100 Å, of strained layer 18 may be removed at aninterface 105 between strained layer 18 and relaxed layer portion 80.This may be achieved by overetching after relaxed layer portion 80 isremoved. Alternatively, this removal of strained layer 18 may beperformed by a standard microelectronics clean step such as an RCA SC1,i.e., hydrogen peroxide, ammonium hydroxide, and water (H₂O₂+NH₄OH+H₂O),which at, e.g., 80° C. may remove silicon. This silicon removal mayremove any misfit dislocations that formed at the original strainedlayer 18/relaxed layer 80 interface 105 if strained layer 18 was grownabove the critical thickness. The critical thickness may be defined asthe thickness of strained layer 18 beyond which it becomes energeticallyfavorable for the strain in the layer to partially relax via theintroduction of misfit dislocations at interface 105 between strainedlayer 18 and relaxed layer 16. Thus, the method illustrated in FIGS. 1-7provides a technique for obtaining strained layers above a criticalthickness without misfit dislocations that may compromise theperformance of deeply scaled MOSFET devices.

[0063] Referring to FIG. 12, in some embodiments, handle wafer 50 mayhave a structure other than a dielectric layer 52 disposed over asemiconductor substrate 54. For example, a bulk relaxed substrate 400may comprise a bulk material 410 such as a semiconductor material, e.g.,bulk silicon. Alternatively, bulk material 410 may be a bulk dielectricmaterial, such as Al₂O₃ (e.g., alumina or sapphire) or SiO₂ (e.g.,quartz). Epitaxial wafer 8 may then be bonded to handle wafer 400 (asdescribed above with reference to FIGS. 1-6), with strained layer 18being bonded to the bulk material 410 comprising handle wafer 400. Inembodiments in which bulk material 410 is a semiconductor, to facilitatethis semiconductor-semiconductor bond, a hydrophobic clean may beperformed, such as an HF dip after an RCA SC1 clean.

[0064] Referring to FIG. 13, after bonding and further processing (asdescribed above), a strained-semiconductor-on-semiconductor (SSOS)substrate 420 is formed, having strained layer 18 disposed in contactwith relaxed substrate 400. The strain of strained layer 18 is notinduced by underlying relaxed substrate 400, and is independent of anylattice mismatch between strained layer 18 and relaxed substrate 400. Inan embodiment, strained layer 18 and relaxed substrate 400 include thesame semiconductor material, e.g., silicon. Relaxed substrate 400 mayhave a lattice constant equal to a lattice constant of strained layer 18in the absence of strain. Strained layer 18 may have a strain greaterthan approximately 1×10⁻³. Strained layer 18 may have been formed byepitaxy, and may have a thickness T₅ of between approximately 20 Å-1000Å, with a thickness uniformity of better than approximately ±5%. Surface92 of strained layer 18 may have a surface roughness of less than 20 Å.

[0065] Referring to FIG. 14, in an embodiment, after fabrication of theSSOI structure 100 including semiconductor substrate 54 and dielectriclayer 52, it may be favorable to selectively relax the strain in atleast a portion of strained layer 18. This could be accomplished byintroducing a plurality of ions by, e.g., ion implantation after aphotolithography step in which at least a portion of the structure ismasked by, for example, a photoresist feature 500. Ion implantationparameters may be, for example, an implant of Si ions at a dose of1×10¹⁵-1×10¹⁷ ions-cm⁻², at an energy of 5-75 keV. After ionimplantation, a relaxed portion 502 of strained layer 18 is relaxed,while a strained portion 504 of strained layer 18 remains strained.

[0066] The bonding of strained silicon layer 18 to dielectric layer 52has been experimentally demonstrated. For example, strained layer 18having a thickness of 54 nanometers (nm) along with ˜350 nm ofSi_(0.70)Ge_(0.30) have been transferred by hydrogen exfoliation to Sihandle wafer 50 having dielectric layer 52 formed from thermal SiO₂ witha thickness of approximately 100 nm. The implant conditions were4×10¹⁶/cm³ H₂ ⁺ dose at 75 keV. The anneal procedure was 1 hour at 550°C. to split the SiGe layer, followed by a 1 hour, 800° C. strengtheninganneal. The integrity of strained Si layer 18 and good bonding todielectric layer 52 after layer transfer and anneal were confirmed withcross-sectional transmission electron microscopy (XTEM). An SSOIstructure 100 was characterized by XTEM and analyzed via Ramanspectroscopy to determine the strain level of the transferred strainedSi layer 18. An XTEM image of the transferred intermediate SiGe/strainedSi/SiO₂ structure showed transfer of the 54 nm strained Si layer 18 and˜350 nm of the Si_(0.70)Ge_(0.30) relaxed layer 16. Strained Si layer 18had a good integrity and bonded well to SiO₂ 54 layer after theannealing process.

[0067] XTEM micrographs confirmed the complete removal of relaxed SiGelayer 16 after oxidation and HF etching. The final structure includesstrained Si layer 18 having a thickness of 49 nm on dielectric layer 52including SiO₂ and having a thickness of 100 nm.

[0068] Raman spectroscopy data enabled a comparison of the bonded andcleaved structure before and after SiGe layer 16 removal. Based on peakpositions the composition of the relaxed SiGe layer and strain in the Silayer may be calculated. See, for example, J. C. Tsang, et al., J. Appl.Phys. 75 (12) p. 8098 (1994), incorporated herein by reference. Thefabricated SSOI structure 100 had a clear strained Si peak visible at˜511 cm⁻¹. Thus, the SSOI structure 100 maintained greater than 1%tensile strain in the absence of the relaxed SiGe layer 16. In addition,the absence of Ge—Ge, SiGe, and Si—Si relaxed SiGe Raman peaks in theSSOI structure confirmed the complete removal of SiGe layer 16.

[0069] In addition, the thermal stability of the strained Si layer wasevaluated after a 3 minute 1000° C. rapid thermal anneal (RTA) tosimulate an aggregate thermal budget of a CMOS process. A Ramanspectroscopy comparision was made of SSOI structure 100 as processed andafter the RTA step. A scan of the as-bonded and cleaved sample prior toSiGe layer removal was used for comparision. Throughout the SSOIstructure 100 fabrication processs and subsequent anneal, the strainedSi peak was visible and the peak position did not shift. Thus, thestrain in SSOI structure 100 was stable and was not diminished bythermal processing. Furthermore, bubbles or flaking of the strained Sisurface 18 were not observed by Nomarski optical microscopy after theRTA, indicating good mechanical stability of SSOI structure 100.

[0070] The invention may be embodied in other specific forms withoutdeparting from the spirit or essential characteristics thereof. Theforegoing embodiments are therefore to be considered in all respectsillustrative rather than limiting on the invention described herein.Scope of the invention is thus indicated by the appended claims ratherthan by the foregoing description, and all changes which come within themeaning and range of equivalency of the claims are intended to beembraced therein.

What is claimed is:
 1. A structure comprising: a first substrate havinga dielectric layer disposed thereon; and a first strained semiconductorlayer disposed in contact with the dielectric layer.
 2. The structure ofclaim 1 wherein the strained semiconductor layer comprises at least oneof a group II, a group III, a group IV, a group V, and a group VIelement.
 3. The structure of claim 2 wherein the strained semiconductorlayer comprises silicon.
 4. The structure of claim 3 wherein thestrained semiconductor layer is substantially free of germanium, and anyother layer disposed in contact with the strained semiconductor layer issubstantially free of germanium.
 5. The structure of claim 2 wherein thestrained semiconductor layer comprises germanium.
 6. The structure ofclaim 2 wherein the strained semiconductor layer comprises silicongermanium.
 7. The structure of claim 2 wherein the strainedsemiconductor layer comprises gallium arsenide.
 8. The structure ofclaim 2 wherein the strained semiconductor layer comprises indiumphosphide.
 9. The structure of claim 2 wherein the strainedsemiconductor layer comprises zinc selenide.
 10. The structure of claim1 wherein the strained semiconductor layer is tensilely strained. 11.The structure of claim 1 wherein the strained semiconductor layer iscompressively strained.
 12. The structure of claim 1 wherein thestrained semiconductor layer comprises a strained portion and a relaxedportion.
 13. The structure of claim 1, further comprising: a secondstrained semiconductor layer in contact with the first strainedsemiconductor layer.
 14. The structure of claim 13 wherein the firststrained semiconductor layer is compressively strained and the secondstrained semiconductor layer is tensilely strained.
 15. The structure ofclaim 13 wherein the first strained semiconductor layer is tensilelystrained and the second strained semiconductor layer is compressivelystrained.
 16. The structure of claim 1, further comprising: a transistorincluding a source region and a drain region disposed in a portion ofthe strained semiconductor layer; a gate disposed above the strainedsemiconductor layer and between the source and drain regions; and a gatedielectric layer disposed between the gate and the strainedsemiconductor layer.
 17. The structure of claim 1 wherein the strainedsemiconductor layer has been formed on a second substrate, has beendisposed in contact with the dielectric layer by bonding, and has alower dislocation density than an initial dislocation density of thestrained semiconductor layer as formed.
 18. The structure of claim 17wherein the initial dislocation density has been lowered by etching. 19.The structure of claim 1 wherein the strained semiconductor layer hasbeen grown with an initial dislocation density and has a dislocationdensity less than the initial dislocation density.
 20. The structure ofclaim 1 wherein the strained semiconductor layer has been formed byepitaxy.
 21. The structure of claim 1 wherein the strained semiconductorlayer has a thickness uniformity of better than approximately ±5%. 22.The structure of claim 1 wherein the strained layer has a thicknessselected from a range of approximately 20 angstroms-1000 angstroms. 23.The structure of claim 1 wherein the strained layer has a surfaceroughness of less than approximately 20 angstroms.
 24. The structure ofclaim 1 wherein the substrate comprises silicon.
 25. The structure ofclaim 1 wherein the substrate comprises germanium.
 26. The structure ofclaim 1 wherein the substrate comprises silicon germanium.
 27. Astructure comprising: a relaxed substrate comprising a bulk material;and a strained layer disposed in contact with the relaxed substrate,wherein the strain of the strained layer is not induced by theunderlying substrate and the strain is independent of a lattice mismatchbetween the strained layer and the relaxed substrate.
 28. The structureof claim 27 wherein the bulk material comprises a first semiconductormaterial.
 29. The structure of claim 27 wherein the strained layercomprises a second semiconductor material.
 30. The structure of claim 29wherein the bulk material comprises a first semiconductor material. 31.The structure of claim 30 wherein the first semiconductor material isessentially the same as the second semiconductor material.
 32. Thestructure of claim 31 wherein the first semiconductor material and thesecond semiconductor material comprise silicon.
 33. The structure ofclaim 27 wherein a lattice constant of the relaxed substrate is equal toa lattice constant of the strained layer in the absence of said strain.34. The structure of claim 27 wherein the strain of the strained layeris greater than approximately 1×10⁻³.
 35. The structure of claim 27wherein the strained layer has been formed by epitaxy.
 36. The structureof claim 27 wherein the strained layer has a thickness uniformity ofbetter than approximately ±5%.
 37. The structure of claim 27 wherein thestrained layer has a thickness selected from a range of approximately 20angstroms-1000 angstroms.
 38. The structure of claim 27 wherein thestrained layer has a surface roughness of less than approximately 20angstroms.
 39. The structure of claim 27, further comprising: atransistor including a source region and a drain region disposed in aportion of the strained semiconductor layer; a gate contact disposedabove the strained semiconductor layer and between the source and drainregions; and a gate dielectric layer disposed between the gate contactand the strained semiconductor layer.
 40. A structure comprising: asubstrate comprising a dielectric material; and a strained semiconductorlayer disposed in contact with the dielectric material.
 41. Thestructure of claim 40 wherein the dielectric material comprisessapphire.
 42. The structure of claim 40 wherein the semiconductor layerhas been formed on a second substrate, has been disposed in contact withthe dielectric material by bonding, and has a lower dislocation densitythan an initial dislocation density of the semiconductor layer asformed.
 43. The structure of claim 42 wherein the initial dislocationdensity has been lowered by etching.
 44. The structure of claim 40wherein the semiconductor layer has been formed by epitaxy.
 45. A methodfor forming a structure, the method comprising: providing a firstsubstrate having a first strained semiconductor layer formed thereon;bonding the first strained semiconductor layer to an insulator layerdisposed on a second substrate; and removing the first substrate fromthe first strained semiconductor layer, the strained semiconductor layerremaining bonded to the insulator layer.
 46. The method of claim 45wherein the strained semiconductor layer is tensilely strained.
 47. Themethod of claim 45 wherein the strained semiconductor layer iscompressively strained.
 48. The method of claim 45 wherein the strainedsemiconductor layer comprises a surface layer after the removal of thefirst substrate.
 49. The method of claim 45 wherein the strainedsemiconductor layer comprises a buried layer after the removal of thefirst substrate.
 50. The method of claim 45 wherein removing the firstsubstrate from the strained semiconductor layer comprises cleaving. 51.The method of claim 50 wherein cleaving comprises implantation of anexfoliation species through the strained semiconductor layer to initiatecleaving.
 52. The method of claim 51 wherein the exfoliation speciescomprises at least one of hydrogen and helium.
 53. The method of claim50 wherein providing the first substrate comprises providing the firstsubstrate having a second strained layer disposed between the substrateand the first strained layer, the second strained layer acting as acleave plane during cleaving.
 54. The method of claim 53 wherein thesecond strained layer comprises a compressively strained layer.
 55. Themethod of claim 54 wherein the compressively strained layer comprisesSi_(1−x)Ge_(x).
 56. The method of claim 45 wherein providing the firstsubstrate comprises providing the first substrate having a relaxed layerdisposed between the substrate and the first strained layer.
 57. Themethod of claim 56, further comprising: planarizing the relaxed layerprior to forming the first strained semiconductor layer.
 58. The methodof claim 57, further comprising: after planarizing the relaxed layer,forming a relaxed semiconductor regrowth layer thereon.
 59. The methodof claim 45, further comprising: forming a dielectric layer over thefirst strained semiconductor layer prior to bonding the first strainedsemiconductor layer to an insulator layer.
 60. The method of claim 45wherein removing the first substrate from the strained semiconductorlayer comprises mechanical grinding.
 61. The method of claim 45 whereinbonding comprises achieving a high bond strength at a low temperature.62. The method of claim 61 wherein the bond strength is greater than orequal to about 1000 milliJoules/meter squared (mJ/m²).
 63. The method ofclaim 61 wherein the temperature is less than approximately 600° C. 64.The method of claim 61 wherein bonding comprises plasma activation of asurface of the first semiconductor layer prior to bonding the firstsemiconductor layer.
 65. The method of claim 64 wherein plasmaactivation comprises use of at least one of an ammonia (NH₃), an oxygen(O₂), an argon (Ar), and a nitrogen (N₂) source gas.
 66. The method ofclaim 61 wherein bonding comprises planarizing a surface of the firstsemiconductor layer prior to bonding the first semiconductor layer. 67.The method of claim 66 wherein planarizing comprises chemical-mechanicalpolishing.
 68. The method of claim 45, further comprising: relaxing aportion of the first strained semiconductor layer.
 69. The method ofclaim 68 wherein the portion of the first strained semiconductor layeris relaxed by introducing a plurality of ions into the portion of thefirst strained semiconductor layer.
 70. The method of claim of claim 45,further comprising: forming a transistor by forming a gate dielectriclayer above a portion of the strained semiconductor layer; forming agate contact above the gate dielectric layer; and forming a sourceregion and a drain region in a portion of the strained semiconductorlayer, proximate the gate dielectric layer.
 71. A method for forming astructure, the method comprising: providing a substrate having a relaxedlayer disposed over a first strained layer, the relaxed layer inducingstrain in the first strained layer; and removing at least a portion ofthe relaxed layer selectively with respect to the first strained layer.72. The method of claim 71 wherein providing the substrate comprisesbonding the first strained layer to the substrate.
 73. The method ofclaim 72 wherein the first strained layer is bonded to an insulatorlayer disposed on the substrate.
 74. The method of claim 71, furthercomprising: before providing the substrate, forming the first strainedlayer over the relaxed layer on another substrate.
 75. The method ofclaim 71 wherein the portion of the relaxed layer is removed byoxidation.
 76. The method of claim 71 wherein the portion of the relaxedlayer is removed by a wet chemical etch.
 77. The method of claim 71wherein the portion of the relaxed layer is removed by a dry etch. 78.The method of claim 71 wherein the portion of the relaxed layer isremoved by chemical-mechanical polishing.
 79. The method of claim 71,further comprising: after removal of at least a portion of the relaxedlayer, planarizing the strained layer.
 80. The method of claim 79wherein planarizing the strained layer comprises chemical-mechanicalpolishing.
 81. The method of claim 79 wherein planarizing the strainedlayer comprises an anneal.
 82. The method of claim 81 wherein the annealis performed at a temperature greater than 800° C.
 83. The method ofclaim 71 wherein providing the substrate comprises providing thesubstrate having an etch stop layer disposed between the relaxed layerand the strained layer.
 84. The method of claim 83 wherein the etch stoplayer is compressively strained.
 85. The method of claim 83 wherein thestrained layer comprises silicon, the relaxed layer comprises silicongermanium, and the etch stop layer comprises silicon germanium carbon.86. The method of claim 83 wherein the relaxed layer comprisesSi_(1−y)Ge_(y), the etch stop layer comprises Si_(1−x)Ge_(x), and x isgreater than y.
 87. The method of claim 86 wherein x is approximately0.5 and y is approximately 0.2.
 88. The method of claim 83 wherein theetch stop layer enables an etch selectivity to the relaxed layer ofgreater than 10:1.
 89. The method of claim 88 wherein the etch stoplayer enables an etch selectivity to the relaxed layer of greater than100:1.
 90. The method of claim 83 wherein the etch stop layer has athickness selected from a range of about 20 angstroms to about 1000angstroms.
 91. The method of claim 71 wherein providing the substratecomprises forming the relaxed layer over a graded layer.
 92. A methodfor forming a structure, the method comprising: providing a firstsubstrate having a dielectric layer disposed thereon; forming asemiconductor layer on a second substrate, the semiconductor layerhaving an initial misfit dislocation density; bonding the semiconductorlayer to the dielectric layer; removing the second substrate, thesemiconductor layer remaining bonded to the dielectric layer; andreducing the misfit dislocation density in the semiconductor layer. 93.The method of claim 92 wherein the misfit dislocation density is reducedby removing a portion of the semiconductor layer.
 94. The method ofclaim 93 wherein the portion of the semiconductor layer is removed byetching.
 95. The method of claim 93, further comprising: after removinga portion of the semiconductor layer to reduce misfit dislocationdensity, forming a regrowth layer over the semiconductor layer withoutincreasing misfit dislocation density.
 96. The method of claim 95wherein the regrowth layer is formed by epitaxy.
 97. A method forforming a structure, the method comprising: providing a first substratehaving a dielectric layer disposed thereon; forming a semiconductorlayer on a second substrate, the semiconductor layer having an initialmisfit dislocation density; bonding the semiconductor layer to thedielectric layer; removing the second substrate, the semiconductor layerremaining bonded to the dielectric layer; and growing a regrowth layerover the semiconductor layer.
 98. The method of claim 97 wherein thesemiconductor layer and the regrowth layer comprise the samesemiconductor material.
 99. The method of claim 97 wherein thesemiconductor layer and the regrowth layer together have a misfitdislocation density not greater than the initial misfit dislocationdensity.
 100. A method for forming a structure, the method comprising:providing a first substrate having a strained layer disposed thereon,the strained layer including a first semiconductor material; bonding thestrained layer to a second substrate, the second substrate comprising abulk material; and removing the first substrate from the strained layer,the strained layer remaining bonded to the bulk semiconductor material,wherein the strain of the strained layer is not induced by the secondsubstrate and the strain is independent of lattice mismatch between thestrained layer and the second substrate.
 101. The method of claim 100wherein the bulk material comprises a second semiconductor material.102. The method of claim 101 wherein the first semiconductor material issubstantially the same as the second semiconductor material.
 103. Themethod of claim 100 wherein the second substrate comprises silicon. 104.The method of claim 100 wherein the strained semiconductor layercomprises silicon.
 105. A method for forming a structure, the methodcomprising: providing a first substrate having a semiconductor layerdisposed over a strained layer; bonding the semiconductor layer to aninsulator layer disposed on a second substrate; and removing the firstsubstrate from the strained layer, the semiconductor layer remainingbonded to the insulator layer.
 106. The method of claim 105 wherein thesemiconductor layer is substantially relaxed.
 107. The method of claim105 wherein the semiconductor layer comprises at least one of a groupII, a group III, a group IV, a group V, and a group VI element.
 108. Themethod of claim 105 wherein the strained layer comprises at least one ofa group II, a group III, a group IV, a group V, and a group VI element.109. The method of claim 107 wherein the semiconductor layer comprisesgermanium and the strained layer comprises silicon.